1. Field of the Invention
This invention relates to semiconductor technologies, and, more particularly, to an interposer and a packaging substrate including the interposer.
2. Description of Related Art
With the rapid development of electronic industry, electronic products are designed to be low-profiled and compact-sized and have a variety of functionality, and can operate at a high speed. To meet the requirements, an electronic product is provided with more and more electronic elements, and a conventional 2D planar integration technique (e.g., side-by-side) evolves into a 3D IC technique. The 3D IC technique integrates a plurality of chips in a 3D space vertically, to achieve the objective of miniaturization. The 3D IC technique differs from the 2D IC technique in that the 3D IC technique employs conductive structures that conduct upper side and lower side of a chip and thus shortens the length of traces provided on the chip.
Since the 3D IC technique is not mature yet, a 2.5D IC technique acts as a transitional technology. The 2.5D IC technique solves the problem of the prior art that the reliability is reduced due to the mismatch between coefficients of thermal expansion (CTE) of the chip and a packaging substrate by providing an interposer between the chip and the packaging substrate. Since the interposer and the chip are made of similar materials, and have approximately the same CTEs, the mismatch problem can thus be solved.
FIGS. 1A-1C illustrate a method of fabricating an interposer according to the prior art.
As shown in FIG. 1A, a plurality of through vias 100 are formed on a complete sheet of a glass body 10.
As shown in FIG. 1B, a metal material is formed in the through vias 100 to form conductive through vias 11.
As shown in FIG. 1C, a redistribution layer (RDL) 12 is formed on an upper side of the glass body 10, a lower side of the glass body 10 is polished to expose the conductive through vias 11, and another redistribution layer 12′ is formed on the lower side of the glass body 10 and exposed surfaces of the conductive through vias 11, such that the interposer 1 is fabricated. The redistribution layers 12 and 12′ are electrically connected to the conductive through vias 11. A plurality of conductive pads 120 are disposed on the upper-side redistribution layer 12. A plurality of conductive pads 120′ are disposed on the lower-side redistribution layer 12′.
In a subsequent flip-chip process, as shown in FIG. 1D, a singulation process is performed on the interposer 1 along a cut route L shown in FIG. 1C, and the singulated interposer 1 is disposed between the packaging substrate 8 and a semiconductor chip 9. Bottom ends of the conductive through vias 11 are electrically connected to the packaging substrate 8 via the conductive pads 120′. The conductive pads 120 disposed on the upper-side redistribution layer 12 are electrically connected to the semiconductor chip 9.
In the prior art, the interposer 1 is made of a single material (i.e., the glass body 10). As a thin interposer 1 is popular in the market, the glass body 10 has to have a thickness reduced accordinly. However, too thin the glass body 10 is likely to be cracked, and has a yield rate less than 50% . In the prior art, the thickness of the glass body 10 of the interposer 1 has to be more than 100 μm. Therefore, the interposer 1 cannot be thinned any further.
Therefore, how to solve the problem of the prior art is becoming an urgent issue in the art.